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NCP3012 Synchronous PWM Controller
The NCP3012 is a PWM device designed to operate from a wide input range and is capable of producing an output voltage as low as 0.8 V. The NCP3012 provides integrated gate drivers and an internally set 75 kHz oscillator. The NCP3012 has an externally compensated transconductance error amplifier with an internally fixed soft-start. The NCP3012 incorporates output voltage monitoring with a Power Good pin to indicate that the system is in regulation. The dual function SYNC pin synchronizes the device to a higher frequency (Slave Mode) or outputs a 180 out-of-phase clock signal to drive another NCP3012 (Master Mode). Protection features include lossless current limit and short circuit protection, output overvoltage and undervoltage protection, and input undervoltage lockout. The NCP3012 is available in a 14-pin TSSOP package.
Features
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14 1 TSSOP-14 DT SUFFIX CASE 948G
* * * * * * * * * * *
Input Voltage Range from 4.7 V to 28 V 75 kHz Operation 0.8 V $1.0% Reference Voltage Buffered External +1.25 V Reference Current Limit and Short Circuit Protection Power Good Enable/Disable Pin Input Undervoltage Lockout External Synchronization Output Overvoltage and Undervoltage Protection This is a Pb-Free Device
MARKING DIAGRAM
14 3012 ALYWG G
1 3012= Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
Typical Applications
* Set Top Box * Power Modules * ASIC / DSP Power Supply
VIN CBST CIN EN PG VREF SYNC RREF RC CC2 C C1 COMP VCC BST HSDR VSW LSDR R ISET GND FB Q2 RFB1 CO RFB2 Q1 LO VOUT
PIN CONNECTIONS
VREF EN NC SYNC PG COMP FB (TOP VIEW) VCC BST HSDR VSW NC LSDR GND
ORDERING INFORMATION
Device Package Shipping NCP3012DTBR2G TSSOP-14 2500 / Tape & Reel (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
CREF
Figure 1. Typical Application Circuit
(c) Semiconductor Components Industries, LLC, 2010
May, 2010 - Rev. 0
1
Publication Order Number: NCP3012/D
NCP3012
VCC
INTERNAL BIAS EN PG ENABLE/ POWER GOOD LOGIC POR/STARTUP VC THERMAL SD BOOST CLAMP BST
SYNC OSCILLATOR CLK/ DMAX/ SOFT START RAMP 1.5 V + - REF OTA FB + - + - PWM COMP GATE DRIVE LOGIC
LEVEL SHIFT VCC CURRENT LIMIT ISET VC SAMPLE & HOLD
HSDR VSW
VREF
1.25 V REFERENCE
COMP
LSDR
OOV OUV
BST_CHRG GND
Figure 2. NCP3012 Block Diagram
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NCP3012
PIN FUNCTION DESCRIPTION
Pin 1 2 Pin Name VREF EN Description The VREF pin is the output for a 1.25 V reference (1 mA max). A 100 kW resistor in parallel with a 1 mF ceramic capacitor must be connected from this pin to GND to ensure external reference stability. The EN pin is the enable/disable input. A logic high on this pin enables the device. This pin has also an internal current source pull up. A 10 kW resistor should be connected in series with this pin if VEN is externally biased from a separate supply. Not Connected The dual function SYNC pin synchronizes the device to a higher frequency (Slave Mode). Alternately, it outputs an 85 kHz clock signal with 180 of phase shift (Master Mode). Connect a 60 kW resistor from SYNC to GND to enable Master Mode. No resistor is required for Slave Mode. The Power Good pin is an open drain output that is low when the regulated output voltage is beyond the "Power Good" upper and lower thresholds. Otherwise, it is a high impedance pin. The COMP pin connects to the output of the Operational Transconductance Amplifier (OTA) and the positive terminal of the PWM comparator. This pin is used in conjunction with the FB pin to compensate the voltage mode control feedback loop. The FB pin is connected to the inverting input of the OTA. This pin is used in conjunction with the COMP pin to compensate the voltage mode control feedback loop. Ground Pin The LSDR pin is connected to the output of the low side driver which connects to the gate of the low side N-FET. It is also used to set the threshold of the current limit circuit (ISET) by connecting a resistor from LSDR to GND. Not Connected The VSW pin is the return path for the high side driver. It is also used in conjunction with the VCC pin to sense current in the high side MOSFET. The HSDR pin is connected to the output of the high side driver which connects to the gate of the high side N-FET. The BST pin is the supply rail for the gate drivers. A capacitor must be connected between this pin and the VSW pin. The VCC pin is the main voltage supply input. It is also used in conjunction with the VSW pin to sense current in the high side MOSFET.
3 4
NC SYNC
5 6
PG COMP
7 8 9
FB GND LSDR
10 11 12 13 14
NC VSW HSDR BST VCC
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NCP3012
ABSOLUTE MAXIMUM RATINGS (measured vs. GND pin 8, unless otherwise noted)
Rating High Side Drive Boost Pin Boost to VSW differential voltage COMP Enable Feedback High-Side Driver Output Low-Side Driver Output Power Good Synchronization Main Supply Voltage Input External Reference Switch Node Voltage Maximum Average Current VCC, BST, HSDRV, LSDRV, VSW, GND REF EN SYNC PG Operating Junction Temperature Range (Note 1) Maximum Junction Temperature Storage Temperature Range Thermal Characteristics (Note 2) TSSOP-14 Plastic Package Thermal Resistance Junction-to-Air Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb-Free (Note 3) Symbol BST BST-VSW COMP EN FB HSDR LSDR PG SYNC VCC VREF VSW Imax VMAX 45 13.2 5.5 5.5 5.5 40 13.2 5.5 5.5 40 5.5 40 130 7.1 2.5 11 4 -40 to +140 +150 -55 to +150 VMIN -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.6 Unit V V V V V V V V V V V V mA
TJ TJ(MAX) Tstg
C C C
RqJA RF
190 260 Peak
C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The maximum package power dissipation limit must not be exceeded.
PD +
T J(max) * T A R qJA
2. When mounted on minimum recommended FR-4 or G-10 board 3. 60-180 seconds minimum above 237C.
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NCP3012
ELECTRICAL CHARACTERISTICS (-40C < TJ < +125C, VCC = 12 V, for min/max values unless otherwise noted)
Characteristic Input Voltage Range SUPPLY CURRENT Quiescent Supply Current VCC Supply Current VCC Supply Current UNDER VOLTAGE LOCKOUT UVLO Rising Threshold UVLO Falling Threshold OSCILLATOR Oscillator Frequency Ramp-Amplitude Voltage Ramp Valley Voltage PWM Minimum Duty Cycle Maximum Duty Cycle Soft Start Ramp Time EXTERNAL VOLTAGE REFERENCE VREF Voltage VREF Line Regulation VREF Load Regulation Short Circuit Output Current ENABLE Enable Threshold High Enable Threshold Low Enable Source Current POWER GOOD Power Good High Threshold Power Good Low Threshold Power Good Low Voltage SYNC SYNC Input High Threshold SYNC Output High SYNC Output Low Phase Delay SYNC Drive Current (Sourcing) Master Threshold Current Master Frequency 4. 5. 6. 7. (Note 4) 10 mA load - - - - - 5.0 70 - 5.0 90 200 1.6 14.4 85 2.0 - - - - 25 100 V V mV mA mA kHz VCC = 12 V VCC = 12 V VCC = 12 V, IPG = 4 mA 0.72 0.65 0.13 0.89 0.71 0.22 1.06 0.75 0.35 V V V - 1.0 20 - - 50 3.4 - 90 V V mA IREF = 1 mA VCC = 4.7 V - 28 V IREF = 0 mA to 1.5 mA VREF = 0 V 1.14 -1 -2 4.5 1.25 - -0.2 5.7 1.35 +1 +2 7.0 V % % mA VFB = VCOMP - 82 - 7 86 14 - - - % % ms TJ = +25C, 4.7 V v VCC v 28 V TJ = -40C to +125C, 4.7 V v VCC v 28 V Vpeak - Valley 65 62 - 0.44 75 75 1.5 0.8 85 88 - 0.96 kHz kHz V V VCC Rising Edge VCC Falling Edge 3.8 3.5 4.3 4.0 4.7 4.3 V V EN = 0 VCC = 12 V VFB = 0.75 V, Switching, VCC = 4.7 V VFB = 0.75 V, Switching, VCC = 28 V - - - 2.5 5.8 6.0 4.0 8.0 12 mA mA mA Conditions - Min 4.7 Typ Max 28 Unit V
Guaranteed by design. The voltage sensed across the high side MOSFET during conduction. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 MW. This is not a protection feature.
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NCP3012
ELECTRICAL CHARACTERISTICS (-40C < TJ < +125C, VCC = 12 V, for min/max values unless otherwise noted)
Characteristic ERROR AMPLIFIER (GM) Transconductance Open Loop dc Gain Output Source Current Output Sink Current FB Input Bias Current Feedback Voltage TJ = 25 C -40C < TJ < +125C, 4.7 V < VIN < 28 V COMP High Voltage COMP Low Voltage OUTPUT VOLTAGE FAULTS Feedback OOV Threshold Feedback OUV Threshold OVER CURRENT ISET Source Current Current Limit Set Voltage (Note 5) GATE DRIVERS AND BOOST CLAMP HSDRV Pullup Resistance HSDRV Pulldown Resistance LSDRV Pullup Resistance LSDRV Pulldown Resistance HSDRV falling to LSDRV Rising Delay LSDRV Falling to HSDRV Rising Delay Boost Clamp Voltage THERMAL SHUTDOWN Thermal Shutdown Hysteresis 4. 5. 6. 7. (Notes 4 and 7) (Notes 4 and 7) - - 150 15 - - C C VCC = 8 V and VBST = 7.5 V VSW = GND, 100 mA out of HSDR pin VCC = 8 V and VBST = 7.5 V VSW = GND, 100 mA into HSDR pin VCC = 8 V and VBST = 7.5 V VSW = GND, 100 mA out of LSDR pin VCC = 8 V and VBST = 7.5 V VSW = GND, 100 mA into LSDR pin VCC and VBST = 8 V VCC and VBST = 8 V VIN = 12 V, VSW = GND, VCOMP = 1.3 V 4.0 2.0 3.0 1.0 50 60 5.5 10.5 5.0 8.9 2.8 85 85 7.5 20 11.5 16 6.0 110 120 9.6 W W W W ns ns V RSET = 22.2 kW 7.0 140 14 240 18 360 mA mV 0.8 0.55 1.0 0.59 1.1 0.65 V V VFB = 0.75 V VFB = 0.85 V (Notes 4 and 6) 0.9 - 45 45 - 0.792 0.788 4.0 - 1.33 70 70 70 0.5 0.8 0.8 4.4 60 1.9 - 100 100 500 0.808 0.812 5.0 - mS dB mA mA nA V V V mV Conditions Min Typ Max Unit
Guaranteed by design. The voltage sensed across the high side MOSFET during conduction. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 MW. This is not a protection feature.
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NCP3012
TYPICAL PERFORMANCE CHARACTERISTICS
806 804 802 800 798 796 794 792 -40 -25 -10 5 20 35 50 65 80 95 110 125 fSW (kHz) VFB (mV) Vin = 12 V, 28 V 90 85 80 Vin = 12 V, 28 V 75 70 65 60 -40 -25 -10 Vin = 5 V
Vin = 5 V
5
20
35
50
65
80
95 110 125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 3. Feedback Reference Voltage vs. Input Voltage and Temperature
7.0 6.5 ICC, SWITCHING (mA) 6.0 5.5 5.0 4.5 4.0 -40 -25 -10 Vin = 5 V 5 20 35 50 65 80 95 110 125 Vin = 28 V ICC, DISABLED (mA) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2
Figure 4. Switching Frequency vs. Input Voltage and Temperature
Vin = 28 V
Vin = 12 V
Vin = 5 V
Vin = 12 V
1.0 -40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 5. Supply Current vs. Input Voltage and Temperature
1.39 1.375 1.36 1.345 1.315 1.30 1.27 1.255 1.24 -40 -25 -10 5 20 35 50 65 80 95 110 125 1.285 4.0 Vin = 12 V, 28 V UVLO (V) gm (mS) 1.33 4.2 Vin = 5 V 4.3 4.4
Figure 6. Supply Current (Disabled) vs. Input Voltage and Temperature
UVLO Rising Threshold
4.1
UVLO Falling Threshold
3.9 -40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 7. Transconductance vs. Input Voltage and Temperature
Figure 8. Input Undervoltage Lockout vs. Temperature
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NCP3012
TYPICAL PERFORMANCE CHARACTERISTICS
1100 OOV, Vin = 5 - 28 V THRESHOLD VOLTAGE (mV) 1000 900 800 700 600 500 -40 -25 -10 PG_Lower, Vin = 5 - 28 V OUV, Vin = 5 - 28 V PG_Upper, Vin = 5 - 28 V VPG (mV) 350 325 300 275 250 225 200 175 5 20 35 50 65 80 95 110 125 150 -40 -25 -10 5 20 35 50 65 80 95 110 125 Vin = 5, 12, 28 V IPG = 4 mA
TEMPERATURE (C)
TEMPERATURE (C)
Figure 9. Output Voltage Thresholds vs. Input Voltage and Temperature
3.5 3.25 3.0 2.75 VEN (V) 2.5 2.25 2.0 1.75 1.5 1.25 Vin = 5 V 5 20 35 50 65 80 95 110 125 1.0 -40 -25 -10 Falling Threshold Vin = 12 V, 28 V Rising Threshold Vin = 12 V, 28 V Vin = 5 V IEN (mA) 70 65 60 55 50 45 40 35
Figure 10. Power Good Output Low Voltage vs. Input Voltage and Temperature
Vin = 5, 12, 28 V
30 -40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 11. Enable Thresold vs. Input Voltage and Temperature
2.0 1.8 Vin = 12 V, 28 V VSYNC (V) 1.6 Vin = 5 V 1.4 1.2 1.0 -40 -25 -10
Figure 12. Enable Pullup Current vs. Input Voltage and Temperature
1000 950 VALLEY VOLTAGE (mV) 900 850 800 750 700 650 600 550 500 450 400 -40 -25 -10 Vin = 5 - 28 V
5
20
35
50
65
80
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 13. SYNC Threshold vs. Input Voltage and Temperature
Figure 14. Valley Voltage vs. Input Voltage and Temperature
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NCP3012
TYPICAL PERFORMANCE CHARACTERISTICS
1.26 1.255 1.25 VREFE (V) 1.245 1.24 1.235 1.23 -40 -25 -10 VREFE_load-reg (%) 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 5 20 35 50 65 80 95 110 125 -1.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Vin = 12 V, 28 V Vin = 5 V Vin = 5 V Vin = 12 V, 28 V
TEMPERATURE (C)
TEMPERATURE (C)
Figure 15. External Reference Voltage vs. Input Voltage and Temperature
14.0 13.8
Figure 16. External Reference Voltage vs. Input Voltage and Temperature
ISET (mA)
13.6 13.4 13.2 13.0 -40 -25 -10
Vin = 12 V, 28 V
Vin = 5 V
5
20
35
50
65
80
95 110 125
TEMPERATURE (C)
Figure 17. Current Limit Set Current vs. Temperature
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NCP3012
DETAILED DESCRIPTION
OVERVIEW
The NCP3012 operates as a 75 kHz, voltage-mode, pulse-width-modulated, (PWM) synchronous buck converter. It drives high-side and low-side N-channel power MOSFETs. The NCP3012 incorporates an internal boost circuit consisting of a boost Clamp and boost diode to provide supply voltage for the high side MOSFET Gate driver. The NCP3012 also integrates several protection features including input undervoltage lockout (UVLO), output undervoltage (OUV), output overvoltage (OOV), adjustable high-side current limit (ISET and ILIM), and thermal shutdown (TSD). The NCP3012 includes a Power Good (PG) open drain output which flags out of regulation conditions. The operational transconductance amplifier (OTA) provides a high gain error signal which is compared to the internal ramp signal using the PWM comparator. This results in a voltage mode PWM feedback stage. The PWM signal is sent to the internal gate drivers to modulate MOSFET on and off times. The gate driver stage incorporates symmetrical fixed non-overlap time between the high-side and low-side MOSFET gate drives. The NCP3012 has a dual function Master/Slave SYNC pin In Slave mode, the NCP3012 synchronizes to an external clock signal. In Master mode, the NCP3012 can output a phase shifted clock signal to drive another master slave equipped power stage to provide a 180 switching relationship between the power stages. This can help to reduce the required input filter capacitance in multi-stage power converters. The external 1.25 V reference voltage (VREF) is provided for system level use. It remains active even when the NCP3012 is disabled.
POR and UVLO
threshold. The device remains in Standby if enable is not asserted following the 50 ms time period.
Enable/Disable
The device has an enable pin (EN) with internal 50 mA pullup current. This gives the user the option of driving EN with a push-pull or open-drain/collector enable signal. When driving EN with an external logic supply a 10 kW series current limiting resistor must be placed in series with EN. See Figure 18. The maximum enable threshold is 3.4 V. If no external drive voltage is available, the internal pullup can be used to enable the device, and an open drain/collector input, such as a MOSFET or BJT can be used to disable the device. A capacitor connected between EN and ground can be used with the internal pullup current source to provide a fixed delay to turn-on and turn off. See Equation 1.
V EN 10 kW
DISABLE ENABLE
EN
Enable Logic
- or-
ENABLE DISABLE
-or-
ENABLE DISABLE
Figure 18. Enable Circuits: Push-Pull, Open-Drain, or Open-Collector I PU T EN_DLY V EN_TH
The device contains an internal Power On Reset (POR) and input Undervoltage Lockout (UVLO) that inhibits the internal logic and the output stage from operating until VCC reaches their respective predefined voltage levels. The internal logic takes approximately 50 ms to check the SYNC pin and determine if the device is in Master mode or Slave mode once the voltage at VCC exceeds the rising UVLO
C EN_DLY +
(eq. 1)
CEN_DLY = Delay Capacitance (F) IPU = Pullup Current VEN_TH = Enable Input High Threshold Voltage TEN_DLY = Desired Delay Time
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NCP3012
Startup and Shutdown
Once enable is asserted the device begins its startup process. Closed-loop soft-start begins after a 400 ms delay wherein the boost capacitor is charged, and the current limit threshold is set. During the 400 ms delay the OTA output is set to just below the valley voltage of the internal ramp. This is done to reduce delays and to ensure a consistent pre soft-start condition. The device increases the internal reference from 0 V to 0.8 V in 32 discrete steps while maintaining closed loop regulation at each step. Some overshoot may be evident at the start of each step depending on the voltage loop phase margin and bandwidth. See Figure 19. The total soft-start time is 14 ms.
The soft-stop process begins once the EN pin voltage goes below the input low threshold. Soft-stop decreases the internal reference from 0.8 V - 0 V in 32 steps as with Soft-Start. Soft-Stop finishes with one "last" high side gate pulse at half the period of the prior pulse. This helps ensure positive inductor current following turn off at light loads, which prevents negative output voltage. Enable low during Soft-Start will result in Soft-Stop down counting from that step. Likewise, Enable high during Soft-Stop will result in Soft-Start up counting from that step.
0.8 V Output Voltage
25 mV Steps
32 Voltage Steps
Internal Reference Voltage Internal Ramp OTA Output 0 .7V 0V
Figure 19. Soft-Start Details
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NCP3012
Master/Slave Synchronization
The SYNC pin performs two functions. The first function is to identify if the device is a master or a slave. The second function is to either synchronize to an external clock
VIN MASTER SYNC 1
(Slave Mode) or provide an external clock that is shifted by 180 from the high side switch (Master Mode). The typical application circuit for this is shown in Figure 20.
HSDR
VIN SYNC 2 SLAVE
HSDR
60kW
Figure 20. Master Slave Typical Application
Upon initial power up, the device determines if it is a Master or Slave by applying 1.25 V to the SYNC pin and determining whether the current draw from the pin is greater than the Master Threshold Current (ISYNCTRIP). If ISYNCTRIP is exceeded then the device enters master mode. If the current is less than ISYNCTRIP the device enters slave mode. Once identified as a Master, the device switching frequency is increased by 15%. See Equation 2.
R Master +
SYNC ref ISYNC TRIP
(eq. 2)
RMaster = Master Select Resistor (W) SYNCref = Sync Reference Voltage (V) ISYNCTRIP = Master Threshold Current (A)
Master HSDRV 0-50% Duty Cycle Slave HSDRV
Pulse Detect Vref = 1.25 V SYNC1 Voltage Vref = 1.25 V SYNC 2 Voltage ITRIP = 10 mA SYNC 1 Current SYNC 2 Current Input Voltage Indication of Master Indication of Slave Time > 40 ms
Master Detection
Hold Result
0-50% Duty Cycle
Time > 40 ms
40 ms Slave Pull Down Turn on
0 mA
Figure 21. Master Slave Typical Waveforms
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NCP3012
The master slave identification begins when input voltage is applied prior to POR. Upon application of input voltage, the device waits for input pulses for a minimum of 40 ms as shown in Figure 21. During the pulse detection period if concurrent edges occur on the SYNC pin from an external source, the device enters slave mode and skips the master detection sequence. The device will remain in the detected state until power is cycled.
Current Sensor
the ramp signal. The equation for calculating the remaining ramp height is shown below:
V RAMP + VRAMP typ * F nom F SYNC 1.5 V * 75 kHz 100 kHz [ 1.125 V
(eq. 3)
OOV, OUV, and Power Good
1.21 V
Master Detect & Hold
SYNC
SYNC_in
SYNC_out
Figure 22. External Synchronization
GND
The device can sync to frequencies that are 15% to 60% higher than the nominal switching frequency. If an external sync pulse is present at the SYNC pin prior to input voltage application to the device, then no additional external components are needed. If the external clock is not present following power on reset of the device, the voltage on the SYNC pin will determine whether the device is a master or a slave. If the external clock source is meant to start after device operation, its off state should be high or tristate. It is also important to note that the slope of the internal ramp is fixed and synchronizing to a faster clock which will truncate
The output voltage of the buck converter is monitored at the Feedback pin of the output power stage. Four comparators are placed on the feedback node of the OTA to monitor the operating window of the feedback voltage as shown in Figures 23 and 24. All comparator outputs are ignored during the soft-start sequence as soft-start is regulated by the OTA and false trips would be generated. Further, the Power Good pin is held low until the comparators are evaluated. After the soft-start period has ended, if the feedback is below the reference voltage of comparator 4 (0.6 < VFB), the output is considered "undervoltage," the device will initiate a restart, and the Power Good pin remains low with a 55 W pulldown resistance. If the voltage at the Feedback pin is between the reference voltages of comparator 4 and comparator 3 (0.60 < VFB < 0.72), then the output voltage is considered "power not good low" and the Power Good pin remains low. When the Feedback pin voltage rises between the reference voltages of comparator 3 and comparator 2 (0.72 < VFB < 0.88), then the output voltage is considered "Power Good" and the Power Good pin is released. If the voltage at the Feedback pin is between the reference voltages of comparator 2 and comparator 1 (0.88 < VFB < 1.00), the output voltage is considered "power not good high" and the power good pin is pulled low with a 55 W pulldown resistance. Finally, if the feedback voltage is greater than comparator 1 (1.0 < VFB), the output voltage is considered "overvoltage," the Power Good pin will remain low, and the device will latch off. To clear a latch fault, input voltage must be recycled. Graphical representation of the OOV, OUV, and Power Good pin functionality is shown in Figures 25 and 26.
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NCP3012
Soft Start Complete
V2 = Vref * 125%
Comparator 1
Power Good
V4 = Vref * 110%
Comparator 2
Restart LOGIC
FB
V5 = Vref * 90%
Comparator 3 Latch off
V7= Vref * 75% Vref = 0.8 V
Comparator 4
Figure 23. OOV, OUV, and Power Good Circuit Diagram
Trip Level Tolerance 2% Hysteresis = 5 mV Trip Level Tolerance 2% Hysteresis = 5 mV
OOVP & Power Good = 0 Voov = Vref * 125% Power Good = 0 Power Not good High Vtrip_pg = Vref * 110% Power Good = 1 Vref = 0.8 V
Trip Level Tolerance 2% Hysteresis = 5 mV Trip Level Tolerance 2% Hysteresis = 5 mV
Power Good = 1 Vtrip_pg = Vref * 90% Power Good = 0 Power Not Good Low Vouv = Vref * 75% OUVP & Power Good = 0
Figure 24. OOV, OUV, and Power Good Window Diagram
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NCP3012
1.0 V (vref * 125 %) 0.88 V (vref * 110 %) 0.8 V ( vref * 100 %) 0.72 V (vref * 90%) 0.60 V (vref * 75%)
FB Voltage
Latch off
Power Good
Power Good Pin
Reinitiate Softstart
Softstart Complete
Figure 25. Powerup Sequence and Overvoltage Latch
1.0 V (vref *125%) 0.88 V (vref *110%) 0.8 V (vref *100%) 0.72 V (vref *90%) 0.60 V (vref *75%)
FB Voltage Latch off
Power Good
Power Good
Reinitiate Softstart
Softstart Complete
Figure 26. Powerup Sequence and Undervoltage Soft-Start
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NCP3012
CURRENT LIMIT AND CURRENT LIMIT SET Overview
The NCP3012 uses the voltage drop across the High Side MOSFET during the on time to sense inductor current. The
ILimit block consists of a voltage comparator circuit which compares the differential voltage across the VCC Pin and the VSW Pin with a resistor settable voltage reference. The sense portion of the circuit is only active while the HS MOSFET is turned ON.
VIN VCC
Ilim Out
VSense Itrip Ref
HSDR
VSW
Switch Cap
CONTROL
Iset 13 uA LSDR
DAC / COUNTER
6
Vset RSet
Itrip Ref-63 Steps, 6.51 mV/step
Figure 27. Iset / ILimit Block Diagram Current Limit Set
The ILimit comparator reference is set during the startup sequence by forcing a typically 13 mA current through the low side gate drive resistor. The gate drive output will rise to a voltage level shown in the equation below:
V set + I set * R set
(eq. 4)
Where ISET is 13 mA and RSET is the gate to source resistor on the low side MOSFET. This resistor is normally installed to prevent MOSFET leakage from causing unwanted turn on of the low side MOSFET. In this case, the resistor is also used to set the ILimit trip level reference through the ILimit DAC. The Iset process takes approximately 350 ms to complete prior to Soft-Start stepping. The scaled voltage level across the ISET resistor is converted to a 6 bit digital value and stored as the trip value. The binary ILimit value is scaled and converted to the analog ILimit reference voltage through a DAC counter. The DAC has 63 steps in 6.51 mV increments equating to a maximum sense voltage of 403 mV. During the Iset period
prior to Soft-Start, the DAC counter increments the reference on the ISET comparator until it crosses the VSET voltage and holds the DAC reference output to that count value. This voltage is translated to the ILimit comparator during the ISense portion of the switching cycle through the switch cap circuit. See Figure 27. Exceeding the maximum sense voltage results in no current limit. Steps 0 to 10 result in an effective current limit of 0 mV.
Current Sense Cycle
Figure 28 shows how the current is sampled as it relates to the switching cycle. Current level 1 in Figure 28 represents a condition that will not cause a fault. Current level 2 represents a condition that will cause a fault. The sense circuit is allowed to operate below the 3/4 point of a given switching cycle. A given switching cycle's 3/4 Ton time is defined by the prior cycle's Ton and is quantized in 10 ns steps. A fault occurs if the sensed MOSFET voltage exceeds the DAC reference within the 3/4 time window of the switching cycle.
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NCP3012
Trip: Vsense > Itrip Ref at 3/4 Point
No Trip: Vsense < Itrip Ref at 3/4 Point
Itrip Ref Vsense
Ton-2
3/4
Ton-1
3/4
Current Level 1 Current Level 2
3/4 Point Determined by Prior Cycle
1/4 1/2 3/4 1/4 1/2 3/4
Ton-1
Ton
Each switching cycle's Ton is counted in 10 nS time steps. The 3/4 sample time value is held and used for the following cycle's limit sample time
Figure 28. ILimit Trip Point Description Soft-Start Current limit Boost Clamp Functionality
During soft-start the ISET value is doubled to allow for inrush current to charge the output capacitance. The DAC reference is set back to its normal value after soft-start has completed. The ILimit block can lose accuracy if there is excessive VSW voltage ringing that extends beyond the 1/2 point of the high-side transistor on-time. Proper snubber design and keeping the ratio of ripple current and load current in the 10-30% range can help alleviate this as well.
Current Limit VSW Ringing
A current limit trip results in completion of one switching cycle and subsequently half of another cycle Ton to account for negative inductor current that might have caused negative potentials on the output. Subsequently the power MOSFETs are both turned off and a 4 soft-start time period wait passes before another soft-start cycle is attempted.
Iave vs Trip Point
The boost circuit requires an external capacitor connected between the BST and VSW pins to store charge for supplying the high and low-side gate driver voltage. This clamp circuit limits the driver voltage to typically 7.5 V when VIN > 9 V, otherwise this internal regulator is in dropout and typically VIN - 1.25 V. The boost circuit regulates the gate driver output voltage and acts as a switching diode. A simplified diagram of the boost circuit is shown in Figure 29. While the switch node is grounded, the sampling circuit samples the voltage at the boost pin, and regulates the boost capacitor voltage. The sampling circuit stores the boost voltage while the VSW is high and the linear regulator output transistor is reversed biased.
VIN
8.9V
The average load trip current versus RSET value is shown the equation below:
I AveTRIP + I set R set R DS(on) * 1 V IN * V OUT 4 L V OUT V IN 1 F SW
(eq. 5)
Switch Sampling Circuit
BST
VSW LSDR
Where: L = Inductance (H) ISET = 13 mA RSET = Gate to Source Resistance (W) RDS(on) = On Resistance of the HS MOSFET (W) VIN = Input Voltage (V) VOUT = Output Voltage (V) FSW = Switching Frequency (Hz)
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Figure 29. Boost Circuit
NCP3012
Reduced sampling time occurs at high duty cycles where the low side MOSFET is off for the majority of the switching period. Reduced sampling time causes errors in the regulated voltage on the boost pin. High duty cycle / input voltage induced sampling errors can result in increased boost ripple voltage or higher than desired DC boost voltage. Figure 30 outlines all operating regions. The recommended operating conditions are shown in Region 1 (Green) where a 0.1 mF, 25 V ceramic capacitor can be placed on the boost pin without causing damage to the device or MOSFETS. Larger boost ripple voltage occurring over several switching cycles is shown in Region 2 (Yellow). The boost ripple frequency is dependent on the output capacitance selected. The ripple voltage will not damage the device or $12 V gate rated MOSFETs. Conditions where maximum boost ripple voltage could damage the device or $12 V gate rated MOSFETs can be seen in Region 3 (Orange). Placing a boost capacitor that is no greater than 10X the input capacitance of the high side MOSFET on the boost pin limits the maximum boost voltage < 12 V. The typical drive waveforms for Regions 1, 2 and 3 (green, yellow, and orange) regions of Figure 30 are shown in Figure 31.
Boost Voltage Levels Normal Operation Increased Boost Ripple (Still in Specification) Increased Boost Ripple Capacitor Optimization Required
28 26 24 22 In p u t V o lt a g e 20 18 16 14 12 10 8 6 4 2 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 11.5V 71% Region 1 Region 2 Maxi mum Max Duty Duty Cycle Cycle 22V Region 3
Duty Cycle
Figure 30. Safe Operating Area for Boost Voltage with a 0.1 mF Capacitor
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NCP3012
7.5V
VIN
VBOOST 7.5V 0V Maximum Normal VIN 7.5V
VBOOST 7.5V 0V Maximum Normal VIN 7.5V
VBOOST 7.5V 0V
Figure 31. Typical Waveforms for Region 1 (top), Region 2 (middle), and Region 3 (bottom)
To illustrate, a 0.1 mF boost capacitor operating at > 80% duty cycle and > 22.5 V input voltage will exceed the specifications for the driver supply voltage. See Figure 32.
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NCP3012
Boost Voltage 18 16 14 12 Boost Voltage (V) 10 8 6 4 2 0 4.5 Voltage Ripple Maximum Allowable Voltage Maximum Boost Voltage
6.5
8.5
10.5
12.5
14.5 16.5 18.5 Input Voltage (V)
20.5
22.5
24.5
26.5
(Clarity on Boost Max and Ripple Def)
Figure 32. Boost Voltage at 80% Duty Cycle Inductor Selection V OUT ) V LSD V IN * V HSD ) V LSD 3.3 V 12 V V OUT V IN
(eq. 8)
When selecting the inductor, it is important to know the input and output requirements. Some example conditions are listed below to assist in the process.
Table 1. DESIGN PARAMETERS
Design Parameter Input Voltage Nominal Input Voltage Output Voltage Input ripple voltage Output ripple voltage Output current rating Operating frequency (VIN) (VIN) (VOUT) (VINRIPPLE) (VOUTRIPPLE) (IOUT) (Fsw) Example Value 9 V to 18 V 12 V 3.3 V 300 mV 50 mV 8A 75 kHz
D+
[D+
27.5% +
The ratio of ripple current to maximum output current simplifies the equations used for inductor selection. The formula for this is given in Equation 9.
ra + DI I OUT
(eq. 9)
A buck converter produces input voltage (VIN) pulses that are LC filtered to produce a lower dc output voltage (VOUT). The output voltage can be changed by modifying the on time relative to the switching period (T) or switching frequency. The ratio of high side switch on time to the switching period is called duty cycle (D). Duty cycle can also be calculated using VOUT, VIN, the low side switch voltage drop VLSD, and the High side switch voltage drop VHSD.
F+ D+ T ON T 1 T T OFF T
(eq. 6)
The designer should employ a rule of thumb where the percentage of ripple current in the inductor lies between 10% and 40%. When using ceramic output capacitors the ripple current can be greater thus a user might select a higher ripple current, but when using electrolytic capacitors a lower ripple current will result in lower output ripple. Now, acceptable values of inductance for a design can be calculated using Equation 10.
L+ V OUT I OUT @ ra @ F SW 3.3 V 8 A @ 25% @ 75 kHz @ (1 * D) 22 mH
(eq. 10)
+
@ (1 * 27.5%)
The relationship between ra and L for this design example is shown in Figure 33.
(* D +
(eq. 7)
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NCP3012
100 95 90 18 Vin 85 80 75 70 65 60 55 12 Vin 50 45 40 35 30 25 20 9 V in 15 10 5 10% 15% Vout = 3.3 V
I PP +
V OUT(1 * D) L OUT @ F SW
(eq. 14)
20% 25% 30% Ripple Current Ratio (%)
35%
40%
Ipp is the peak to peak current of the inductor. From this equation it is clear that the ripple current increases as LOUT decreases, emphasizing the trade-off between dynamic response and ripple current. The power dissipation of an inductor consists of both copper and core losses. The copper losses can be further categorized into dc losses and ac losses. A good first order approximation of the inductor losses can be made using the DC resistance as they usually contribute to 90% of the losses of the inductor shown below:
LP CU + I RMS 2 @ DCR
(eq. 15)
L, INDUCTANCE (mH)
Figure 33. Ripple Current Ratio vs. Inductance
To keep within the bounds of the parts maximum rating, calculate the RMS current and peak current.
I RMS + I OUT @ +8A@ I PK + I OUT @ 1 ) 1 ) ra 8.02 A 12 1) (0.25) 2 12 (0.25) 2
(eq. 12)
2
The core losses and ac copper losses will depend on the geometry of the selected core, core material, and wire used. Most vendors will provide the appropriate information to make accurate calculations of the power dissipation then the total inductor losses can be capture buy the equation below:
LP tot + LP CU_DC ) LP CU_AC ) LP Core (eq. 16) Input Capacitor Selection
(eq. 11)
ra 9.0 A + 8 A @ 1 ) 2
The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET, so it must have a low ESR to minimize the losses. The RMS value of this ripple is:
Iin RMS + I OUT @ D @ (1 * D)
(eq. 17)
An inductor for this example would be around 3.3 mH and should support an rms current of 8.02 A and a peak current of 9.0 A. The final selection of an output inductor has both mechanical and electrical considerations. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space-constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by Equation 13.
SlewRate LOUT + V IN * V OUT L OUT 0.4 12 V * 3.3 V A + ms 22 mH
(eq. 13)
D is the duty cycle, IinRMS is the input RMS current, and IOUT is the load current. The equation reaches its maximum value with D = 0.5. Loss in the input capacitors can be calculated with the following equation:
P CIN + ESR CIN @ I IN*RMS
2
(eq. 18)
PCIN is the power loss in the input capacitors and ESRCIN is the effective series resistance of the input capacitance. Due to large dI/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum must be used, it must by surge protected. Otherwise, capacitor failure could occur.
Input Start-up Current
This equation implies that larger inductor values limit the regulator's ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. This results in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator's maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. The peak-to-peak ripple current for the NCP3012 is given by the following equation:
To calculate the input startup current, the following equation can be used.
I INRUSH + C OUT @ V OUT t SS
(eq. 19)
Iinrush is the input current during startup, COUT is the total output capacitance, VOUT is the desired output voltage, and tSS is the soft start interval. If the inrush current is higher than the steady state input current during max load, then the input fuse should be rated accordingly, if one is used.
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NCP3012
Output Capacitor Selection
The important factors to consider when selecting an output capacitor is dc voltage rating, ripple current rating, output ripple voltage requirements, and transient response requirements. The output capacitor must be rated to handle the ripple current at full load with proper derating. The RMS ratings given in datasheets are generally for lower switching frequency than used in switch mode power supplies but a multiplier is usually given for higher frequency operation. The RMS current for the output capacitor can be calculated below:
Co RMS + I O @ ra 12
(eq. 20)
In a typical converter design, the ESR of the output capacitor bank dominates the transient response. It should be noted that DVOUT-DISCHARGE and DVOUT-ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the ESL). Conversely during a load release, the output voltage can increase as the energy stored in the inductor dumps into the output capacitor. The ESR contribution from Equation 21 still applies in addition to the output capacitor charge which is approximated by the following equation:
DV OUT-CHG + Power MOSFET Selection I TRAN
2
@ L OUT
(eq. 26)
C OUT @ V OUT
The maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the equivalent series inductance (ESL) and ESR. The main component of the ripple voltage is usually due to the ESR of the output capacitor and the capacitance selected.
V ESR_C + I O @ ra @ ESR Co ) 1 8 @ F SW @ Co
(eq. 21)
The ESL of capacitors depends on the technology chosen but tends to range from 1 nH to 20 nH where ceramic capacitors have the lowest inductance and electrolytic capacitors then to have the highest. The calculated contributing voltage ripple from ESL is shown for the switch on and switch off below:
V ESLON + ESL @ I PP @ F SW D ESL @ I PP @ F SW (1 * D )
(eq. 22)
Power dissipation, package size, and the thermal environment drive MOSFET selection. To adequately select the correct MOSFETs, the design must first predict its power dissipation. Once the dissipation is known, the thermal impedance can be calculated to prevent the specified maximum junction temperatures from being exceeded at the highest ambient temperature. Power dissipation has two primary contributors: conduction losses and switching losses. The control or high-side MOSFET will display both switching and conduction losses. The synchronous or low-side MOSFET will exhibit only conduction losses because it switches into nearly zero voltage. However, the body diode in the synchronous MOSFET will suffer diode losses during the non-overlap time of the gate drivers. Starting with the high-side or control MOSFET, the power dissipation can be approximated from:
P D_CONTROL + P COND ) P SW_TOT
(eq. 27)
V ESLOFF +
(eq. 23)
The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for the first few microseconds it supplies the current to the load. The controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. During a load step transient the output voltage initially drops due to the current variation inside the capacitor and the ESR (neglecting the effect of the effective series inductance (ESL)).
DV OUT-ESR + DI TRAN @ ESR Co
(eq. 24)
The first term is the conduction loss of the high-side MOSFET while it is on.
P COND + I RMS_CONTROL
2
@ R DS(on)_CONTROL (eq. 28)
Using the ra term from Equation 9, IRMS becomes:
I RMS_CONTROL + I OUT @ D@ 1) ra 2 12
(eq. 29)
The second term from Equation 27 is the total switching loss and can be approximated from the following equations.
P SW_TOT + P SW ) P DS ) P RR
(eq. 30)
A minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to output capacitor discharge is approximated by the following equation:
DV OUT-DISCHG + I TRAN
2
The first term for total switching losses from Equation 30 includes the losses associated with turning the control MOSFET on and off and the corresponding overlap in drain voltage and current.
P SW + P TON ) P TOFF + 1 @ I OUT @ V IN @ f SW @ t ON ) t OFF 2
(eq. 31)
@ L OUT
(eq. 25)
C OUT @ V IN * V OUT
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NCP3012
where:
t ON + Q GD I G1 + Q GD V BST * V TH R HSPU ) R G Q GD V BST * V TH R HSPD ) R G
(eq. 32)
and:
t OFF + Q GD I G2 +
(eq. 33)
Next, the MOSFET output capacitance losses are caused by both the control and synchronous MOSFET but are dissipated only in the control MOSFET.
P DS + 1 @ Q OSS @ V IN @ f SW 2
(eq. 34)
Finally the loss due to the reverse recovery time of the body diode in the synchronous MOSFET is shown as follows:
P RR + Q RR @ V IN @ f SW
(eq. 35)
The low-side or synchronous MOSFET turns on into zero volts so switching losses are negligible. Its power dissipation only consists of conduction loss due to RDS(on) and body diode loss during the non-overlap periods.
P D_SYNC + P COND ) P BODY
(eq. 36)
IG1: output current from the high-side gate drive (HSDR) IG2: output current from the low-side gate drive (LSDR) SW: switching frequency of the converter. VBST: gate drive voltage for the high-side drive, typically 7.5 V. QGD: gate charge plateau region, commonly specified in the MOSFET datasheet VTH: gate-to-source voltage at the gate charge plateau region QOSS: MOSFET output gate charge specified in the data sheet QRR: reverse recovery charge of the low-side or synchronous MOSFET, specified in the datasheet RDS(on)_CONTROL: on resistance of the high-side, or control, MOSFET RDS(on)_SYNC: on resistance of the low-side, or synchronous, MOSFET NOLLH: dead time between the LSDR turning off and the HSDR turning on, typically 85 ns NOLHL: dead time between the HSDR turning off and the LSDR turning on, typically 75 ns Once the MOSFET power dissipations are determined, the designer can calculate the required thermal impedance for each device to maintain a specified junction temperature at the worst case ambient temperature. The formula for calculating the junction temperature with the package in free air is:
T J + T A ) P D @ R qJA
Conduction loss in the low-side or synchronous MOSFET is described as follows:
P COND + I RMS_SYNC
2
@ R DS(on)_SYNC (eq. 37)
where:
I RMS_SYNC + I OUT @ ra 2 ( 1 * D) @ 1 ) 12
(eq. 38)
The body diode losses can be approximated as:
P BODY + V FD @ I OUT @ f SW @ NOL LH ) NOL HL
(eq. 39)
TJ: Junction Temperature TA: Ambient Temperature PD: Power Dissipation of the MOSFET under analysis RqJA: Thermal Resistance Junction-to-Ambient of the MOSFET's package As with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e. worst case MOSFET RDS(on)).
Vth
Figure 34. MOSFET Switching Characteristics
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NCP3012
NOLHL NOLLH
High-Side Logic Signal
Low-Side Logic Signal td(on) RDSmax High-Side MOSFET RDS(on)min tr td(off) tr RDSmax Low-Side MOSFET RDS(on)min td(on) td(off) tf tf
Figure 35. MOSFETs Timing Diagram
Another consideration during MOSFET selection is their delay times. Turn-on and turn-off times must be short enough to prevent cross conduction. If not, there will be conduction from the input through both MOSFETs to ground. Therefore, the following conditions must be met.
t d(ON)_CONTROL ) NOL LH u t d(OFF)_SYNC ) t f_SYNC and
(eq. 40)
response. The goal of the compensation circuit is to provide a loop gain function with the highest crossing frequency and adequate phase margin (minimally 45). The transfer function of the power stage (the output LC filter) is a double pole system. The resonance frequency of this filter is expressed as follows:
f P0 + 1 2 @ p @ L @ C OUT
(eq. 41)
t (ON)_SYNC ) NOL HL u t d(OFF)_CONTROL ) t f _CONTROL
The MOSFET parameters, td(ON), tr, td(OFF) and tf are can be found in their appropriate datasheets for specific conditions. NOLLH and NOLHL are the dead times which were described earlier and are 85 ns and 75 ns, respectively.
Feedback and Compensation
Parasitic Equivalent Series Resistance (ESR) of the output filter capacitor introduces a high frequency zero to the filter network. Its value can be calculated by using the following equation:
f Z0 + 1 2 @ p @ C OUT @ ESR
(eq. 42)
The NCP3012 is a voltage mode buck convertor with a transconductance error amplifier compensated by an external compensation network. Compensation is needed to achieve accurate output voltage regulation and fast transient
Table 2. COMPENSATION TYPES
Zero Crossover Frequency Condition fP0 < fZ0 < f0 < fS/2 fP0 < f0 < fZ0 < fS/2 fP0 < f0 < fS/2 < fZ0
The main loop zero crossover frequency f0 can be chosen to be 1/10 - 1/5 of the switching frequency. Table 2 shows the three methods of compensation.
Compensation Type Type II Type III Method I Type III Method II
Typical Output Capacitor Type Electrolytic, Tantalum Tantalum, Ceramic Ceramic
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NCP3012
Compensation Type II
This compensation is suitable for electrolytic capacitors. Components of the Type II compensation (Figure 36) network can be specified by the following equations:
f Z1 + 0.75 @ f P0 f Z2 + f P0 f P2 + f Z0 f P3 + fS 2
(eq. 47) (eq. 48) (eq. 49) (eq. 50)
Method II is better suited for ceramic capacitors that typically have the lowest ESR available:
f Z2 + f 0 @ f P2 + f 0 @ 1 * sinq max 1 ) sin q max 1 ) sin q max 1 * sin q max
(eq. 51)
(eq. 52) (eq. 53) (eq. 54)
f Z1 + 0.5 @ f Z2 Figure 36. Type II Compensation R C1 + C C1 + C C2 + R1 + 2 @ p @ f 0 @ L @ V RAMP @ V OUT ESR @ V IN @ V ref @ gm 1 0.75 @ 2 @ p @ f P0 @ R C1 1 p @ R C1 @ f S V ref @ R2
(eq. 43)
f P3 + 0.5 @ f S 2 gm
The remaining calculations are the same for both methods.
R C1 u u
(eq. 55) (eq. 56)
(eq. 44)
C C1 +
(eq. 45)
1 2 @ p @ f Z1 @ R C1 1 2 @ p @ f P3 @ R C1 V IN @ R C1
C C2 +
(eq. 46)
(eq. 57)
V OUT * V ref
VRAMP is the peak-to-peak voltage of the oscillator ramp and gm is the transconductance error amplifier gain. Capacitor CC2 is optional.
Compensation Type III
C FB1 + R FB1 + R1 +
2 @ p @ f 0 @ L @ V RAMP @ C OUT 1 2p @ C FB1 @ f P2
(eq. 58)
(eq. 59)
Tantalum and ceramics capacitors have lower ESR than electrolytic, so the zero of the output LC filter goes to a higher frequency above the zero crossover frequency. This requires a Type III compensation network as shown in Figure 37. There are two methods to select the zeros and poles of this compensation network. Method I is ideal for tantalum output capacitors, which have a higher ESR than ceramic:
1 * R FB1 2 @ p @ C FB1 @ f Z2 V
ref
(eq. 60)
R2 +
V OUT * V ref
@ R1
(eq. 61)
If the equation in Equation 62 is not true, then a higher value of RC1 must be selected.
R1 @ R2 @ R FB1 R1 @ R FB1 ) R2 @ R FB1 ) R1 @ R2 u 1 (eq. 62) gm
Figure 37. Type III Compensation
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NCP3012
PACKAGE DIMENSIONS
TSSOP-14 CASE 948G-01 ISSUE B
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 --- 1.20 --- 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_
0.15 (0.006) T U
S
A -V-
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT
7.06 1
0.36
14X
14X
1.26
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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EEE CCC EEE CCC
0.65 PITCH
DIMENSIONS: MILLIMETERS
NCP3012/D

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